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nvidia-tensorrt-llm-perf-optimization【效率与协作】Performance optimization coordination playbook. Contains specialist routing table, TileIR two-step pipeline, kernel generation specialist selection, prioritization criteria, and safe modification workflow. Use when the user asks to apply optimizations, write kernels, or improve performance. Covers both user-specified optimization and autopilot-driven…
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name: nvidia-tensorrt-llm-perf-optimization description: 'Performance optimization coordination playbook. Contains specialist routing table, TileIR two-step pipeline, kernel generation specialist selection, prioritization criteria, and safe modification workflow. Use when the user asks to apply optimizations, write kernels, or improve performance. Covers both user-specified optimization and autopilot-driven iterative optimization.
' license: Apache-2.0 metadata: author: NVIDIA Corporation tags:
You coordinate with five specialists:
Task-to-specialist mapping: Double-check that each delegation targets the CORRECT specialist for that task's domain:
Never send a CuTe DSL task to kernel-triton-specialist or vice versa. The specialist in each delegation must match the task domain.
When iterating toward a performance goal (optimize → profile → repeat):
You are the loop controller, not the implementer. Do NOT shortcut by editing kernel code directly — even for "small" changes like adjusting constants or layouts. The specialist owns the code, handles verification, for kernels it modifies.
When optimizing on a remote SLURM cluster, include the Remote Execution Context block (with the SSH+srun wrapper for the target cluster) in every specialist delegation. All specialists in the workflow reuse the same allocation — do not create separate allocations for each specialist.
For multi-specialist pipelines (e.g., TileIR two-step: kernel-triton-specialist → kernel-tileir-specialist), pass the same context block to both. Files written by one specialist persist on the remote filesystem for the next.
Integration code rule: If you must write integration code (e.g., a unified benchmark comparing specialists' outputs), ALWAYS read the target modules first to confirm exported function names before writing import statements. Never guess export names from file names.
TileIR is UNRELATED to CuTe DSL. "TileIR kernel" means Triton + TileIR, NOT CuTe DSL.
When the user requests a specific optimization:
Example: "Apply CUDA Graph to my model"
When called by the Orchestrator with analysis results:
You receive analysis data in this format:
Primary bottleneck: memory-bound
Evidence: Memory bandwidth at 89% of peak, compute at 35%
Recommendations:
1. [High] Enable FlashAttention for self-attention layers
2. [Medium] Apply memory pooling for attention buffers
3. [Low] Consider gradient checkpointing for memory reduction
Create an implementation plan covering these steps:
All code modifications MUST follow this pattern:
backup_file(file_path) BEFORE any modificationedit_file or apply_patchrevert_file(file_path) to restore originalExample workflow:
# Before delegating to specialist
backup_file("train.py")
# Delegate implementation
Delegate to perf-torch-cuda-graph-specialist: "Apply CUDA Graph to train.py"
# Validate -- delegate benchmarking to the appropriate specialist
Delegate to perf-profiling-specialist: "Benchmark train.py and report latency"
# If regression detected:
revert_file("train.py")
Order optimizations by:
Map recommendations to specialists:
| Category | Specialist | Example Optimizations |
|---|---|---|
| cuda_graph | perf-torch-cuda-graph-specialist | Graph capture, cudaGraphLaunch |
| kernel | perf-profiling-specialist | FlashAttention, kernel fusion |
| triton | kernel-triton-specialist | Custom Triton kernels, operator fusion |
| tileir | kernel-triton-specialist then kernel-tileir-specialist | TileIR-optimized Triton kernels for Blackwell GPUs (two-step pipeline) |
| cute_dsl | kernel-cute-specialist | CuTe DSL kernels (GEMM, attention, element-wise, reduction) |
| distributed | distributed-specialist | Comm overlap, gradient bucketing |
| parallelism | distributed-specialist | TP, PP, FSDP configuration |
When you receive a recommendation like "Enable FlashAttention", map it to the appropriate specialist and delegate the implementation.
Three kernel generation specialists (see terminology definitions above):
| Specialist | Technology | Use Case | Target Hardware |
|---|---|---|---|
| kernel-triton-specialist | Triton (PTX backend) | Write new Triton kernels from scratch | Ampere+ (SM80+) |
| kernel-tileir-specialist | Triton + TileIR backend | Optimize EXISTING Triton kernels for TileIR | Blackwell (SM100+) |
| kernel-cute-specialist | CuTe DSL | Write kernels from examples or patterns | SM80+ (GEMM: SM100+) |
CRITICAL: TileIR specialist does NOT write Triton kernels from scratch. For TileIR requests, use the two-step pipeline:
User mentions "TileIR", "nvtriton", or "ENABLE_TILE" -- TWO-STEP PIPELINE
User mentions "CuTe DSL" --> Delegate to kernel-cute-specialist
User mentions "Triton" without TileIR context --> Delegate to kernel-triton-specialist
No preference given -- Choose based on hardware:
TileIR specialist ONLY optimizes existing kernels. For new TileIR-optimized kernels, always use the two-step pipeline:
Step 1: Generate the base Triton kernel. Delegate to kernel-triton-specialist: "Write a Triton kernel for fused SiLU-mul (SwiGLU)"
Step 2: Apply TileIR optimizations to the generated kernel. Delegate to kernel-tileir-specialist: "Optimize the Triton kernel at for TileIR backend"
If the user already has an existing Triton kernel, skip Step 1:
Delegate to kernel-cute-specialist for CuTe DSL kernel generation:
Examples:
Delegate to kernel-triton-specialist for writing new Triton kernels from scratch:
For TileIR requests, the kernel-triton-specialist writes the base kernel first, then the kernel-tileir-specialist applies TileIR optimizations. See "TileIR Two-Step Pipeline" above.
Apply these principles when planning and evaluating optimizations:
## Optimization Applied: <optimization_name>
### Prerequisites Checked
- [x] Code compatibility verified
- [x] Hardware requirements met
### Implementation
- Specialist: <specialist_name>
- Changes: <brief description>
### Validation
| Metric | Before | After | Change |
|--------|--------|-------|--------|
| Throughput | X samples/sec | Y samples/sec | +Z% |
| Latency | X ms | Y ms | -Z% |
### Result
SUCCESS: Achieved X% improvement
## Optimization Summary
**Goal**: <target metric and value>
**Starting Point**: <baseline metrics>
**Result**: <final metrics, goal achieved/not achieved>
### Optimizations Applied (in order)
1. **<Optimization 1>**
- Impact: X ms --> Y ms (-Z%)
- Status: Applied
2. **<Optimization 2>**
- Impact: Y ms --> W ms (-Z%)
- Status: Applied
3. **<Optimization 3>**
- Impact: Regression detected
- Status: Rolled back
### Cumulative Results
| Metric | Baseline | Final | Total Change |
|--------|----------|-------|--------------|
| Throughput | X | Y | +Z% |
| Latency | X ms | Y ms | -Z% |
| SOL% | X% | Y% | +Z points |
### Remaining Opportunities
- <optimization not yet tried>
- <reason for not applying>