brainstorming
brainstorming
You MUST use this before any creative work - creating features, building components, adding functionality, modifying behavior, or planning anything new, in software or out of it (a talk, a business, a renovation).
virtual-memory-paging-and-tlbVirtual memory skill for paging, page tables, and TLB. Use when explaining page faults, multi-level page tables, TLB behavior, or virtual vs physical addressing. Activates on queries about virtual memory, page table, TLB, page fault, mmap paging, or x86-64 paging.
Independent GitHub snapshot · Automated classification · Original documentation governs
Explain virtual memory: paging, multi-level page tables, TLB role, page faults, and address translation — bridging OS kernels, embedded MPU, and performance analysis.
mmap, brk, and demand pagingVirtual address (VA)
├── TLB lookup → physical on hit
└── TLB miss → page table walk → fill TLB
├── valid PTE → physical address
└── invalid → page fault (OS handles)
CR3 → PML4 → PDPT → PD → PT → physical frame
Linux on x86_64 uses 4 KiB pages (default) and optional 2 MiB / 1 GiB huge pages.
| Fault | Typical cause |
|---|---|
| Major | Disk read — file-backed page not in RAM |
| Minor | Zero-fill or COW break |
| Protection | User access to kernel page, W^X violation |
# Linux page fault stats
grep pgfault /proc/vmstat
Large sparse address spaces + random pointer chasing → TLB misses dominate.
Mitigations:
mmap huge pages (MAP_HUGETLB, madvise(MADV_HUGEPAGE))numactl --membind for NUMAMany MCUs use MPU (region-based) not full paging — no TLB, fixed region count. Application processors use MMU + OS.
See skills/platform/riscv-privileged for Sv39/Sv48.
cat /proc/self/maps
pmap -x $
/virtual-memory-paging-and-tlb Explain why 4 KiB random access hurts TLB and hugepage helps
| Symptom | Cause | Fix |
|---|---|---|
| Segfault | Unmapped VA | Fix pointer; check maps |
| Slow mmap workload | TLB thrashing | Huge pages; reduce regions |
| COW spike after fork | Shared pages split on write | Expected; consider MAP_POPULATE |
| W^X fault | JIT without mprotect dance | Separate RW and RX mappings |
| Wrong phys on MCU | No MMU — linear map | Use linker script addresses |
skills/computer-architecture/memory-hierarchy-and-caches — cache after translationskills/kernel-dev/kernel-memory-management — kernel page allocatorskills/kernel/os-dev-scratch — build paging from scratchskills/platform/riscv-privileged — Sv39 page tablesskills/allocators/numa-programming — NUMA and migration