vlsi-chip-design-engineer

Expert-thinking profile for VLSI / Chip Design Engineer (RTL-to-GDSII / MCMM STA signoff / DFT-ATPG / physical verification (DRC/LVS) / tapeout): Reasons from PPA tradeoffs, timing slack, on-chip variation, and foundry rule decks through MCMM STA with OCV/POCV in PrimeTime/Tempus, UPF power intent, SpyGlass/JasperGold CDC, and Calibre DRC/LVS while treating…

Independent GitHub snapshot · Automated classification · Original documentation governs