vivado-timing-closure

Vivado FPGA timing closure and optimization assistant. Covers systematic timing analysis, constraint validation, implementation strategy selection (place_design/phys_opt_design/route_design directives), pblock-based area constraints, RapidWright-assisted netlist optimization, and iterative convergence workflows. Use when users mention timing closure, WNS/TN…

Independent GitHub snapshot · Automated classification · Original documentation governs